// Autogenerated with DRAKON Editor 1.23

module verilog_example (
    // Inputs
    abc, def, jhk);

    // Parameters
    parameter a;
    parameter b;
    parameter c;

    // Inputs
    input reg abc[2:0];
    input wire [1:0] def [2:22];
    input reg jhk;




    // 'always' block from diagram 'always2'

    wire [7:0] a;
    wire [7:0] b;
    wire [2:0] c;

    reg [7:0] qwe;
    reg [3:0] asd;
    reg [2:0] xcz;

    always @(posedge clk or negedge reset_n)
    begin: block_name_here
        if (!reset_n) begin
        end else begin
            // item 65
            if (a > b) begin 
                // item 68
                c = a + b;
            end else begin
                // item 69
                c = b - a;
            end
        end
    end // block_name_here


    // 'always' block from diagram 'always22'

    always @(*)
    begin
        // item 73
        a = b;
        // item 226
        test_val  =  125;
    end


    // 'always' block from diagram 'always55'

    wire [7:0] a;
    wire [7:0] b;
    wire [2:0] c;

    reg [7:0] qwe;
    reg [3:0] asd;
    reg [2:0] xcz;

    always @(posedge clk or negedge reset_n)
    begin: always55
        if (!reset_n) begin
            b <= 0;
            c <= 0;
        end else begin
            // item 238
            test_val  <=  125;
            // item 232
            if (a > b) begin 
                // item 235
                c = a + b;
                // item 239
                test_val1  <=  125;
            end else begin
                // item 236
                e = d + f;
            end
            // item 263
            data_o  <=  { 1'b1, a};
            // item 264
            {c,b,a}  <=  data_i;
        end
    end // always55


    // function 'func' from diagram 'func'

    function [3:0] func;
    parameter integer qwe = 22;
    input [3:0] a;
    input [4:2] b;
    reg [7:0] c;
    begin
        // item 80
        func = a + b;
        // item 970002
        for(i=0;i<10;i++) begin
        // item 99
        b = i;
        // item 250
        // sub: 'sub_func'
        // item 245
        if (abc == def) begin 
            // item 248
            yes
        end else begin
            // item 249
            no
        end
        // end: 'sub_func'
        // item 970003
        end
    end
    endfunction

    // function 'func1' from diagram 'func1'

    function  func1;
    begin
        while (1) begin
            // item 124
            if (a > b) begin 
                // item 251
                func
                // item 176
                if (b < a) begin 
                    break
                end else begin
                    
                end
            end else begin
                // item 127
                a = a + 1;
            end
        end
        // item 223
        test_val  =  125;
    end
    endfunction

    // 'always' block from diagram 'test block'

    wire [7:0] a;
    wire [7:0] b;
    wire [2:0] c;

    reg [7:0] qwe;
    reg [3:0] asd;
    reg [2:0] xcz;

    always @(posedge clk or negedge reset_n)
    begin: block_name_here
        if (!reset_n) begin
            b <= 0;
            c <= 0;
        end else begin
            // item 224
            test_val  <=  125;
            // item 104
            if (a > b) begin 
                // item 107
                c = a + b;
                // item 225
                test_val1  <=  125;
            end else begin
                // item 108
                e = d + f;
            end
        end
    end // block_name_here


    // 'assign' block from diagram 'тест assign'

    localparam P1 = 123;

    wire [7:0] abc;

    reg [3:0] aaa;

    // item 270
    assign abc  =  P1 + 222;
    // item 271
    assign aaa  =  abc + 565;

    // FSM from  diagram 'state machine'

    localparam  [0:0]  // state codes of FSM 'state machine'
        STATE_MACHINE_BRANCH_1 =  1'd0;  // branch 1
    localparam  [0:0]  STATE_MACHINE_HALT_STATE =  1'd1;  // HALT state

    reg  [0:0]  state_machine_state;

    always @(posedge clk or negedge reset_n)
        if (!reset_n) begin
            state_machine_state <= STATE_MACHINE_BRANCH_1;
        end else begin
            case (state_machine_state)
                STATE_MACHINE_BRANCH_1:
                    if (m1 == 2) begin
                        // item 27
                        if (a == b) begin 
                            // item 30
                            state
                        end else begin
                            // item 31
                            state
                        end
                        // item 26
                        state
                        // item 9
                        state_machine_state <= STATE_MACHINE_BRANCH_1;
                    end else if (m2 == 3) begin
                        // item 25
                        state
                        // item 23
                        state_machine_state <= STATE_MACHINE_HALT_STATE;
                    end else begin
                        // item 24
                        state
                        // item 22
                        state_machine_state <= STATE_MACHINE_HALT_STATE;
                    end
                STATE_MACHINE_HALT_STATE: state_machine_state <= STATE_MACHINE_HALT_STATE;
                default: 
                    state_machine_state <= STATE_MACHINE_HALT_STATE;
            endcase // case (state_machine_state)
        end

    // FSM 'fsm_read'  from diagram 'автомат номер два'

    localparam  [1:0]  // state codes of FSM 'fsm_read'
        FSM_READ_BRANCH_11 =  2'd1,  // branch 11
        FSM_READ_BRANCH_35 =  2'd2;  // branch 35

    reg  [1:0]  fsm_read_state;

    always @(posedge clk or negedge reset_n)
    begin: fsm_read
        if (!reset_n) begin
            a <= 23;
            b <= 45;
            fsm_read_state <= FSM_READ_BRANCH_11;
        end else begin
            case (fsm_read_state)
                FSM_READ_BRANCH_11:
                    if (m1 == 22) begin
                        // item 262
                        // sub: 'sub_diag'
                        // item 256
                        if (a == bbb) begin 
                            // item 259
                            qwe<=11;
                            // item 261
                            test_val  <=  125;
                        end else begin
                            // item 260
                            a<=12;
                        end
                        // end: 'sub_diag'
                        // item 140
                        fsm_read_state <= FSM_READ_BRANCH_11;
                    end else if (m2 == 34) begin
                        // item 154
                        ccc<=11;
                        // item 152
                        fsm_read_state <= FSM_READ_BRANCH_35;
                    end else begin
                        // item 151
                        fsm_read_state <= FSM_READ_BRANCH_35;
                    end
                FSM_READ_BRANCH_35:
                    if (qwe) begin
                        // item 170
                        ccc<=11;
                        // item 168
                        fsm_read_state <= FSM_READ_BRANCH_35;
                    end else begin
                        // item 169
                        eeee<=11;
                        // item 167
                        fsm_read_state <= FSM_READ_BRANCH_11;
                    end
                default: 
                    fsm_read_state <= FSM_READ_BRANCH_11;
            endcase // case (fsm_read_state)
        end
    end // fsm_read

    // FSM 'fsm_read'  from diagram 'автомат номер два-2'

    localparam  [2:0]  // state codes of FSM 'fsm_read'
        FSM_READ_BRANCH_11 =  3'd1,  // branch 11
        FSM_READ_BRANCH_35 =  3'd2,  // branch 35
        FSM_READ_BRANCH_77 =  3'd4;  // branch 77

    reg  [2:0]  fsm_read_state;


    reg  [71:0]  fsm_read_state_name;  // ASCII decode of fsm_read_state

    always @(fsm_read_state) begin
        case (fsm_read_state)
             FSM_READ_BRANCH_11:  fsm_read_state_name =  "branch 11";
             FSM_READ_BRANCH_35:  fsm_read_state_name =  "branch 35";
             FSM_READ_BRANCH_77:  fsm_read_state_name =  "branch 77";
            default:  fsm_read_state_name =  "!ERR     ";
        endcase
    end  // decode of fsm_read_state

    always @(posedge clk or negedge reset_n)
    begin: fsm_read
        if (!reset_n) begin
            a <= 23;
            b <= 45;
            fsm_read_state <= FSM_READ_BRANCH_11;
        end else begin
            case (fsm_read_state)
                FSM_READ_BRANCH_11:
                    if (m1 == 22) begin
                        // item 203
                        if (a == bbb) begin 
                            // item 206
                            qwe<=11;
                            // item 189
                            fsm_read_state <= FSM_READ_BRANCH_11;
                        end else begin
                            // item 207
                            a<=12;
                            // item 189
                            fsm_read_state <= FSM_READ_BRANCH_11;
                        end
                    end else if (m2 == 34) begin
                        // item 202
                        ccc<=11;
                        // item 201
                        fsm_read_state <= FSM_READ_BRANCH_35;
                    end else begin
                        // item 151
                        fsm_read_state <= FSM_READ_BRANCH_35;
                    end
                FSM_READ_BRANCH_35:
                    if (qwe) begin
                        // item 213
                        ccc<=11;
                        // item 211
                        fsm_read_state <= FSM_READ_BRANCH_77;
                    end else begin
                        // item 169
                        eeee<=11;
                        // item 167
                        fsm_read_state <= FSM_READ_BRANCH_11;
                    end
                FSM_READ_BRANCH_77:
                    if (ccc<=11;) begin
                        // item 276
                        fsm_read_state <= FSM_READ_BRANCH_35;
                    end else begin
                        $error("Default handler for state 'branch 77' is not defined!");
                    end
                default: 
                    fsm_read_state <= FSM_READ_BRANCH_11;
            endcase // case (fsm_read_state)
        end
    end // fsm_read

    // FSM 'fsm_read222'  from diagram 'автомат номер два-2-2'

    localparam  [1:0]  // state codes of FSM 'fsm_read222'
        FSM_READ222_BRANCH_11 =  2'd1,  // branch 11
        FSM_READ222_BRANCH_35 =  2'd2;  // branch 35

    reg  [1:0]  fsm_read222_state;


    reg  [71:0]  fsm_read222_state_name;  // ASCII decode of fsm_read222_state

    always @(fsm_read222_state) begin
        case (fsm_read222_state)
             FSM_READ222_BRANCH_11:  fsm_read222_state_name =  "branch 11";
             FSM_READ222_BRANCH_35:  fsm_read222_state_name =  "branch 35";
            default:  fsm_read222_state_name =  "!ERR     ";
        endcase
    end  // decode of fsm_read222_state

    always @(posedge clk or negedge reset_n)
    begin: fsm_read222
        if (!reset_n) begin
            a <= 23;
            b <= 45;
            fsm_read222_state <= FSM_READ222_BRANCH_11;
        end else begin
            case (fsm_read222_state)
                FSM_READ222_BRANCH_11:
                    if (m1 == 22) begin
                        // item 305
                        if (a == bbb) begin 
                            // item 308
                            qwe<=11;
                            // item 291
                            fsm_read222_state <= FSM_READ222_BRANCH_11;
                        end else begin
                            // item 309
                            a<=12;
                            // item 291
                            fsm_read222_state <= FSM_READ222_BRANCH_11;
                        end
                    end else if (m2 == 34) begin
                        // item 304
                        ccc<=11;
                        // item 303
                        fsm_read222_state <= FSM_READ222_BRANCH_35;
                    end else begin
                        // item 151
                        fsm_read222_state <= FSM_READ222_BRANCH_35;
                    end
                FSM_READ222_BRANCH_35:
                    if (qwe) begin
                        // item 315
                        ccc<=11;
                        // item 313
                        fsm_read222_state <= FSM_READ222_BRANCH_35;
                    end else begin
                        // item 169
                        eeee<=11;
                        // item 167
                        fsm_read222_state <= FSM_READ222_BRANCH_11;
                    end
                default: 
                    fsm_read222_state <= FSM_READ222_BRANCH_11;
            endcase // case (fsm_read222_state)
        end
    end // fsm_read222


endmodule // verilog_example

